| Code | Width | Height | Ratio | Description |
|---|---|---|---|---|
| QVGA | 320 | 240 | 4:3 | Quarter Video Graphics Array |
| HVGA | 640 | 240 | 8:3 | Half Video Graphics Array |
| VGA | 640 | 480 | 4:3 | Video Graphics Array |
| SVGA | 800 | 600 | 4:3 | Super Video Graphics Array |
| XGA | 1024 | 768 | 4:3 | Extended Graphics Array |
| XGA+ | 1152 | 768 | 3:2 | Extended Graphics Array plus |
| 1152 | 864 | 4:3 | ||
| SXGA | 1280 | 1024 | 5:4 | Super Extended Graphics Array |
| SXGA+ | 1400 | 1050 | 4:3 | Super Extended Graphics Array plus |
| UXGA | 1600 | 1200 | 4:3 | Ultra Extended Graphics Array |
| QXGA | 2048 | 1536 | 4:3 | Quad Extended Graphics Array |
| Code | Width | Height | Ratio | Description |
|---|---|---|---|---|
| WXGA | 1280 | 768 | 5:3 | Wide Extended Graphics Array |
| 1280 | 800 | 16:10 | ||
| 1366 | 768 | ~16:9 | ||
| WXGA+ | 1280 | 854 | ~3:2 | Wide Extended Graphics Array plus |
| 1440 | 900 | 16:10 | ||
| 1440 | 960 | 3:2 | ||
| WSXGA | 1600 | 900 | 16:9 | Wide Super Extended Graphics Array |
| 1600 | 1024 | 16:10 | ||
| WSXGA+ | 1680 | 1050 | 16:10 | Wide Super Extended Graphics Array plus |
| WUXGA | 1920 | 1200 | 16:10 | Wide Ultra Extended Graphics Array |
| WQXGA | 2560 | 1600 | 16:10 | Wide Quad Extended Graphics Array |
| WQUXGA | 3840 | 2400 | 16:10 | Wide Quad Ultra Extended Graphics Array |
| Component | Ideal | Good | Bad | Damage |
| CPU (idle) | <35°C | 35-45°C | 45-50°C | >50°C |
| CPU (50%) | <50°C | 50-65°C | 65-75°C | >75°C |
| CPU (full load) | <60°C | 60-80°C | 80-85°C | >85°C |
| GPU (idle) | <40°C | 40-50°C | 50-60°C | >60°C |
| GPU (50%) | <55-60°C | 60-65°C | 65-70°C | >70°C |
| GPU (full load) | <65°C | 65-80°C | 80-95°C | >95°C |
DIMM stands for dual inline memory module, and SIMM stands for single inline memory module. The gold or tin pins on the lower edge of the front and back of a SIMM are connected, providing a single line of communication paths between the module and the system. The pins on a DIMM are not connected, providing two lines of communication paths between the module and the system, one in the front and one in the back.
Dynamic random-access memory (DRAM) is a type of random-access memory that stores each bit of data in a separate capacitor within an integrated circuit Static random-access memory (SRAM) is a type of semiconductor memory that uses bistable latching circuitry to store each bit. The term static differentiates it from dynamic RAM (DRAM) which must be periodically refreshed. SRAM exhibits data remanence,[1] but it is still volatile in the conventional sense that data is eventually lost when the memory is not powered.
Synchronous dynamic random access memory (SDRAM) is dynamic random access memory (DRAM) that is synchronized with the system bus. Classic DRAM has an asynchronous interface, which means that it responds as quickly as possible to changes in control inputs. SDRAM has a synchronous interface, meaning that it waits for a clock signal before responding to control inputs and is therefore synchronized with the computer's system bus. The clock is used to drive an internal finite state machine that pipelines incoming commands. The data storage area is divided into several banks, allowing the chip to work on several memory access commands at a time, interleaved among the separate banks. This allows higher data access rates than an asynchronous DRAM.
Pipelining means that the chip can accept a new command before it has finished processing the previous one. In a pipelined write, the write command can be immediately followed by another command, without waiting for the data to be written to the memory array. In a pipelined read, the requested data appears after a fixed number of clock cycles after the read command (latency), clock cycles during which additional commands can be sent. (This delay is called the latency and is an important performance parameter to consider when purchasing SDRAM for a computer.) SDRAM is widely used in computers; from the original SDRAM, further generations of DDR (or DDR1) and then DDR2 and DDR3 have entered the mass market, with DDR4 currently being designed and anticipated to be available in 2013.
